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1 ?2016 integrated device technology, inc november 8, 2016 description the 8t49n243 has one fractional-feedback pll that can be used as a jitter attenuator and frequency translator. it is equipped with one integer and one fractional output divider, allowing the generation of up to two different output frequenc ies, ranging from 8khz to 1ghz. these frequencies are completely independent of each other, the input reference frequencies and the crystal reference frequency. the device places virtually no constraints on input to output frequency conversion, supporting all fec rates, including the new revision of itu-t recommendation g.709 (2009), most with 0ppm conversion error. the outputs may select among lvpecl, lvds, hcsl or lvcmos output levels. this makes it ideal to be used in any frequency synthesis application, including 1g, 10g, 40g and 100g synchronous ethernet, otn, and sonet/sdh, including itu-t g.709 (2009) fec rates. the 8t49n243 accepts one differential or single-ended input clock and a fundamental-mode crystal input. the internal pll can lock to the input reference clock or just to the crystal to behave as a frequency synthesizer. a second input reference (fbin) is used as the external feedback input for zero delay buffer functionality. the device monitors both input references for loss of signal (los), and generates an alarm when an input reference failure is detected. the pll has a register-selectable loop bandwidth from 0.2hz to 6.4khz. the device starts up with output q0 set to 10mhz, and output q1 set to 20mhz. loop bandwidth is set to 25hz. input clock, clk is set to 2.5mhz. the device supports output enable inputs and lock and los status outputs. the device is programmable through an i 2 c interface. typical applications ? otn or sonet / sdh equipment ? gigabit and terabit ip switches / routers including synchronous ethernet ? video broadcast features ? supports sdh/sonet and synchronous ethernet clocks including all fec rate conversions ? 375fs rms typical jitter (including spurs): 12khz to 20mhz ? operating modes: synthesizer, jitter attenuator ? operates from a 10mhz to 50mhz fundamental-mode crystal or a 10mhz to 125mhz external oscillator ? accepts one lvpecl, lvds, lvhstl or lvcmos input clock ? accepts frequencies ranging from 8khz to 875mhz ? clock input monitoring ? generates two lvpecl / lvds / hcsl or four lvcmos device outputs ? output frequencies ranging from 8khz up to 1.0ghz (differential) ? output frequencies ranging from 8khz to 250mhz (lvcmos) ? one integer divider ranging from 4 to 786,420 ? three fractional output dividers (see output dividers ) ? programmable loop bandwidth settings from 0.2hz to 6.4khz ? optional fast-lock function ? four general purpose i/o pins with optional support for status & control: ? two output enable control inputs provide control over the device outputs ? lock and loss-of-signal alarm outputs ? open-drain interrupt pin ? register programmable through i 2 c ? full 2.5v or 3.3v supply modes, 1.8v support for lvcmos outputs, gpio and control pins ? -40c to 85c ambient operating temperature ? package: 40qfn, lead-free (rohs 6) 8t49n243 datasheet femtoclock ? ng universal frequency translator
2 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet block diagram figure 1: block diagram
3 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet pin assignments figure 2: pin assignments for 6mm x 6mm 40-lead package pin description table table 1: pin descriptions number name type [a] description 1v cca power analog function supply for core analog functions. 2.5v or 3.3v supported. 2v cca power analog function supply for analog functions associated with the pll. 2.5v or 3.3v supported. 3 gpio[0] i/o pullup general-purpose input-output. lvttl / lvcmos input levels. 4v cco0 power high-speed output supply for output pair q0, nq0. 2.5v or 3.3v supported for differential output types. lvcmos outputs also support 1.8v. 5 q0 o universal clock output. please refer to the output drivers for more details. 6 nq0 o universal clock output. please refer to the output drivers for more details. 7 gpio[1] i/o pullup general-purpose input-output. lvttl / lvcmos input levels. 8 nq1 o universal clock output. please refer to the output drivers for more details. 9 q1 o universal clock output. please refer to the output drivers for more details. 10 v cco1 power high-speed output supply for output pair q1, nq1. 2.5v or 3.3v supported for differential output types. lvcmos outputs also support 1.8v. 11 sdata i/o pullup i 2 c interface bi-directional data. 11 12 13 14 15 16 17 18 19 20 12345678910 31 32 33 34 35 36 37 38 39 40 21 22 23 24 25 26 27 28 29 30 fclk nc nc v cco2 nfclk gpio[2] nc gpio[3] nint v cca clk v cc v ee sclk sdata v cc nclk fbin nfbin s_a1 gpio[0] v cco0 q0 v cca v cca nq0 gpio[1] nq1 q1 v cco1 osco v cca osci v cccs nwp cap cap_ref v cca s_a0 nrst transistor count: 454,200
4 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet 12 sclk i/o pullup i 2 c interface bi-directional clock. 13 v cc power core digital function supply. 2.5v or 3.3v supported. 14 v ee power negative supply voltage. all v ee pins and epad must be connected before any positive supply voltage is applied. 15 v cc power core digital function supply. 2.5v or 3.3v supported. 16 clk i pulldown non-inverting differential clock input. 17 nclk i pullup / pulldown inverting differential clock input. v cc / 2 when left floating (set by internal pull-up / pulldown resistors) 18 fbin i pulldown non-inverting differential feedback clock input. connect to fclk, or the output of an external feedback divider, depending on application. 19 nfbin i pullup / pulldown inverting differential feedback clock input. connect to nfclk, or the output of an external feedback divider, depending on application. v cc / 2 when left floating (set by internal pull-up / pulldown resistors). 20 s_a1 i pulldown i 2 c address bit a1. 21 v cco2 power high-speed output supply voltage for output pair fclk, nfclk. 2.5v or 3.3v supported for differential output types. lvcmos outputs also support 1.8v. 22 fclk o lvds levels differential clock output pair. lvds levels. connect to fbin for the pre-configured frequency. 23 nfclk o lvds levels differential clock output pair. lvds levels. connect to nfbin for the pre-configured frequency. 24 gpio[2] i/o pullup general-purpose input-output. lvttl / lvcmos input levels. 25 nc unused do not connect. 26 nc unused do not connect. 27 nc unused do not connect. 28 gpio[3] i/o pullup general-purpose input-output. lvttl / lvcmos input levels. 29 nint o open-drain with pull-up interrupt output. 30 v cca power analog function supply for analog functions associated with pll. 2.5v or 3.3v supported. 31 nrst i pullup master reset input. lvttl / lvcmos interface levels: 0 = all registers and state machines are reset to their default values 32 v cca power analog function supply for core analog functions. 2.5v or 3.3v supported. 33 osci i crystal input. accepts a 10mhz ? 50mhz reference from a clock oscillator or a 12pf fundamental mode, parallel-resonant crystal. for proper device functionality, a crystal or external oscillator must be connected to this pin. 34 osco o crystal output. this pin must be connected to a crystal. if an oscillator is connected to osci, then this pin must be left unconnected. table 1: pin descriptions number name type [a] description
5 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet 35 nwp i pullup write protect input. lvttl / lvcmos interface levels. 0 = write operations on the serial port will complete normally, but will have no effect except on interrupt registers. 36 v cccs power output supply for control & status pins: gpio[3:0], sdata, sclk, s_a1, s_a0, nint, nwp, nrst 1.8v, 2.5v or 3.3v supported 37 cap analog pll external capacitance. a 0.1f capacitance value across cap and cap_ref pins is recommended. 38 cap_ref analog pll external capacitance. a 0.1f capacitance value across cap and cap_ref pins is recommended. 39 v cca power analog function supply for analog functions associated with pll. 2.5v or 3.3v supported. 40 s_a0 i pulldown i 2 c address bit a0. epad exposed pad power negative supply voltage. all v ee pins and epad must be connected before any positive supply voltage is applied. a. pullup and pulldown refer to internal input resistors. see table 26 , pin characteristics, for typical values. table 1: pin descriptions number name type [a] description
6 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet principles of operation the 8t49n243 can be locked to the input clock and generate a wide range of synchronized output clocks. it could be used for example in either the transmit or receive path of synchronous ethernet equipment. the 8t49n243 accepts one differential or single-ended input clock ranging from 8khz up to 875mhz. it generates up to two output clocks ranging from 8khz up to 1.0ghz. the pll path within the 8t49n243 supports two states: lock and free-run. the lock status may be monitored on register bits and pins. in the locked state, the pll locks to a valid clock input and its output clocks have a frequency accuracy equal to the frequency accur acy of the input clock. in the free-run state, the pll outputs a clock with the same frequency accuracy as the external crystal. upon power up, the pll will enter free-run state, in this state it generates output clocks with the same frequency accuracy as the external crystal. the 8t49n243 continuously monitors the clock input for activity (signal transitions). if no input reference is provide d, the device will remain locked to the crystal in free-run state and will generate output frequencies as a synthesizer. when an input clock has been validated, the pll will transition to the lock state. the device supports conversion of any input frequencies to two different independent output frequencies. the 8t49n243 has a programmable loop bandwidth from 0.2hz to 6.4khz. in default configuration, the device looks for a 2.5mhz input clock. the device starts up with output q0 set to 10mhz and outpu t q1 set to 20mhz. loop bandwidth is set to 25hz. the device monitors both input references and generates an alarm when an input clock failure is detected on either clk or fbin inputs. the device is programmable through an i 2 c interface and may also autonomously read its register settings from an internal one-time programmable (otp) memory. crystal input the crystal input on the 8t49n243 is capable of being driven by a parallel-resonant, fundamental mode crystal with a frequency range of 10mhz ? 50mhz. the oscillator input also supports being driven by a single-ended crystal oscillator or reference clock. the long term drift will depend on the quality of the crystal or oscillator attached to this port. this device provides the ability to double the crystal frequency input into the pll for improved close-in phase noise performan ce. refer to figure 3 . figure 3: doubler block diagram bypass path the crystal input or either reference input (clk or fbin) may be used directly as a clock source for the fclk output dividers. this may only be done for input frequencies of 250mhz or less. 0 x2 1 osc register bit dbl_dis to fclk bypass path to analog pll
7 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet input clock selection the 8t49n243 accepts an input clock with frequencies ranging from 8khz up to 875mhz. the clock input can accept lvpecl, lvds, lvhstl, hcsl or lvcmos inputs using 1.8v, 2.5v or 3.3v logic levels. the clock input does not support transmission of spread-spectrum clocking sources. since this family is intended for high-perfo rmance applications, it will assume input reference sources to have stabilities of + 100ppm or better, except where gapped clock inputs are used. input clock monitor the clock input is monitored for loss of signal (los). if no activity has been detected on the clock input within a user-select able time period then the clock input is considered to be failed and an internal loss-of-signal status flag is set. the user-selectable time per iod has sufficient range to allow a gapped clock missing many consecutive edges to be considered a valid input. user-selection of the clock monitor time-period is based on a counter driven by a monitor clock. the monitor clock is fixed at the frequency of the pll?s vco divided by 8. with a vco range of 3ghz - 4ghz, the monitor clock has a frequency range of 375mhz to 500mhz. the monitor logic for the input reference will count the number of monitor clock edges indicated in the appropriate monitor con trol register. if an edge is received on the input reference being monitored, then the count resets and begins again. if the target edge count is reached before an input reference edge is received, then an internal soft alarm is raised and the count re-starts. during the soft alarm perio d, the pll tracking will not be adjusted. if an input reference edge is received before the count expires for the second time, then the soft alarm status is cleared and the pll will resume adjustments. if the count expires again without any input reference edge being received, then a loss-of -signal alarm is declared. it is expected that for normal (non-gapped) clock operation, users will set the monitor clock count for each input reference to be slightly longer than the nominal period of that input reference. a margin of 2-3 monitor clock periods should give a reasonably quick reaction time and yet prevent false alarms. for gapped clock operation, the user will set the monitor clock count to a few monitor clock periods longer than the longest ex pected clock gap period. the monitor count registers support 17-bit count values, which will support at least a gap length of two clock periods for any supported input reference frequency, with longer gaps being supported for faster input reference frequencies. since gapped clocks usually occur on input reference frequencies above 100mhz, gap lengths of thousands of periods can be supported. using this configuration for a gapped clock, the pll will continue to adjust while the normally expected gap is present, but wi ll freeze once the expected gap length has been exceeded and alarm after twice the normal gap length has passed. once a los on either clk or fbin is detected, the appropriate internal los alarm will be asserted and it will remain asserted u ntil that input clock returns and is validated. validation occurs once 8 rising edges have been received on that input reference. if another er ror condition on the same input clock is detected during the validation time then the alarm remains asserted and the validation period starts ov er. each los flag may also be reflected on one of the gpio[3:0] outputs. changes in status of any reference can also generate an in terrupt if not masked. input to output clock frequency the 8t49n243 is designed to accept any frequency within its input range and generate two different output frequencies that are independent from the input frequencies and from each other. the internal architecture of the device ensures that most translations will res ult in the exact output frequency specified. please contact idt for configuration software or other assistance in determining if a desired confi guration will be supported exactly. synthesizer mode operation the device may act as a frequency synthesizer with the pll generating its operating frequency from just the crystal input. by s etting the syn_mode register bit and setting the state[1:0] field to free-run, no input clock references are required to generate the desi red output frequencies. when operating as a synthesizer, the precision of the output frequency will be < 1ppb for any supported configuration.
8 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet loop filter and bandwidth the 8t49n243 uses one external capacitor of fixed value to support its loop bandwidth. when operating in synthesizer mode a fix ed loop bandwidth of approximately 200khz is provided. when not operating as a synthesizer, the 8t49n243 will support a range of loop bandwidths: 0.2hz, 0.4hz, 0.8hz, 1.6hz, 3.2hz, 6 .4hz, 12hz, 25hz, 50hz, 100hz, 200hz, 400hz, 800hz, 1.6khz or 6.4khz. the device supports two different loop bandwidth settings: acquisition and locked. these loop bandwidths are selected from the list of options described above. if enabled, the acquisition bandwidth is used while lock is being acquired to allow the pll to ?fast-lock?. on ce locked the pll will use the locked bandwidth setting. if the acquisition bandwidth setting is not used, the pll will use the locked bandwidth setting at all times. output dividers the 8t49n243 supports one integer output divider and one fractional output divider. the integer output divider block consists of two divider stages in a series to achieve the desired total output divider ratio. the first stage divider may be set to divide by 4, 5 or 6. the second stage of the divider may be bypassed (i.e. divide-by-1) or programmed to any even divider ratio from 2 to 131,070. the total divide rati os, settings and possible output frequencies are shown in table 2 . an output synchronization via the pll_syn bit is necessary after programming the output dividers to ensure that the outputs are synchronized. fractional output divider programming (q1 and fclk) for the fracn output divider q1 the output divide ratio is given by: ? output divide ratio = (n.f)x2 ? n = integer part: 4, 5, ...(2 18 -1) ? f = fractional part: [0, 1, 2, ...(2 28 -1)]/(2 28 ) for integer operation of these output dividers, n = 3 is also supported for the full output frequency range. the minimum output divide ratio defined above is valid for all clk_sel modes. table 2: output divide ratios 1st-stage divide 2nd-stage divide total divide minimum f out (mhz) maximum f out (mhz) 414 750 1000 5 1 5 600 800 6 1 6 500 666.7 4 2 8 375 500 5 2 10 300 400 6 2 12 250 333.3 4 4 16 187.5 250 5 4 20 150 200 6 4 24 125 166.7 ... 4 131,070 524,280 0.0057 0.0076 5 131,070 655,350 0.0046 0.0061 6 131,070 786,420 0.0038 0.0051
9 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet output divider frequency sources output dividers associated with the q[1:0] outputs take their input frequency directly from the pll. output dividers associated with the fclk outputs can take their input frequencies from the pll, clk or fbin input reference fre quency or the crystal frequency. output drivers the q[1:0] clock outputs are provided with register-controlled output drivers. by selecting the output drive type in the approp riate register, either output can support lvcmos, lvpecl, hcsl or lvds logic levels. the operating voltage ranges of each output is determined by its independent output power pin (v cco ) and thus each can have different output voltage levels. output voltage levels of 2.5v or 3.3v are supported for differential operation and lvcmos operation. in addition, lvcmos output operation supports 1.8v v cco. each output may be enabled or disabled by register bits and/or gpio pins. lvcmos operation when a given output is configured to provide lvcmos levels, then both the q and nq outputs will toggle at the selected output f requency. all the previously described configuration and control apply equally to both outputs. frequency, voltage levels and enable / disabl e status apply to both the q and nq pins. when configured as lvcmos, the q & nq outputs can be selected to be phase-aligned with each other or in verted relative to one another. selection of phase-alignment may have negative effects on the phase noise performance of any part of t he device due to increased simultaneous switching noise within the device. power-saving modes to allow the device to consume the least power possible for a given application, the following functions can be disabled via re gister programming: ? ? ? ?
10 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet general-purpose i/os & interrupts the 8t49n243 provides four general purpose input / output (gpio) pins for miscellaneous status & control functions. each gpio may be configured as either an input or an output. each gpio may be directly controlled from register bits or be used as a predefined function as shown in table 3 . note that the default state prior to configuration being loaded from internal otp will be to set each gpio to input direction to function as an output enable. if used in the fixed function mode of operation, the gpio bits will reflect the real-time status of their respective status bit s as shown in table 3 . the lol alarm will support two modes of operation: ? de-asserts once pll is locked, or ? de-asserts after pll is locked and all internal synchronization operations that may destabilize output clocks are completed. interrupt functionality interrupt functionality includes an interrupt status flag for each of pll loss-of-lock status (lol) and loss-of-signal status for each input (los[1:0]). those status flags are set whenever there is an alarm on their respective functions. the status flag will remain set until the alarm has been cleared and a ?1? has been written to the status flag?s register location or if a reset occurs. each status flag will also have an interrupt enable bit that will determine if that status flag is allowed to cause the device interrupt status to be affected (enabled) or not (disabled). all interrupt enable bits will be in the disabled state after reset. the device interrupt status flag and nint output pin are asser ted if any of the enabled interrupt status flags are set. table 3: gpio configuration [a] a. gpi[x]: general purpose input. logic state on gpio[x] pin is directly reflected in gpi[x] register. lol: loss-of-lock status flag for digital pll. logic-high indicates digital pll not locked. gpo[x]: general purpose output. logic state is determined by value written in register gpo[x]. osel[n]: output enable control signals for outputs qx, nqx. refer to output enable operation section. los[x]: loss-of-signal status flag for input 4eference (0 = clk, 1 = fbin). logic-high indicates input reference failure. gpio pin configured as input configured as output fixed function general purpose fixed function general purpose 3 ? gpi[3] (default) lol gpo[3] 2 ? gpi[2] (default) los[0] gpo[2] 1 osel[1] gpi[1] (def ault) los[1] gpo[1] 0 osel[0] (default) gpi[0] ? gpo[0]
11 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet output enable operation when gpio[1:0] are used as output enable control signals (both gpio0 and gpio1 must be configured as osel[0] and osel[1], respectively), the function of the pins is to select one of four register-based maps that indicate which outputs should be enab led or disabled. figure 4: output enable map operation device hardware configuration the8t49n243 supports an internal one-time programmable (otp) memory that is pre-programmed at the factory with one complete dev ice configuration. this pre-programmed configuration will be loaded into the device?s registers on power-up or reset. these default register settings can be over-written using the serial programming interface once reset is complete. any configur ation written via the serial programming interface needs to be re-written after any power cycle or reset. please contact idt if a different facto ry-programmed configuration is desired. device start-up & reset behavior the 8t49n243 has an internal power-up reset (por) circuit and a master reset input pin nrst. if either is asserted, the device will be in the reset state. for highly programmable devices, it?s common practice to reset the device immediately after the initial power-on sequence. idt recommends connecting the nrst input pin to a programmable logic source for optimal functionality. it is recommended that a minimum pulse width of 10ns be used to drive the nrst input. while in the reset state (nrst input asserted or por active), the device will operate as follows: ? all registers will return to & be held in their default states as indicated in the applicable register description. ? all internal state machines will be in their reset conditions. ? the serial interface will not respond to read or write cycles. ? the gpio signals will be configured as output enable inputs. ? all clock outputs will be disabled. ? all interrupt status and interrupt enable bits will be cleared, negating the nint signal. upon the later of the internal por circuit expiring or the nrst input negating, the device will exit reset and begin self-confi guration. the device will load its configuration using the data stored in the internal one-time programmable (otp) memory. once the full configuration has been loaded, the device will respond to accesses on the serial port and will attempt to lock th e pll to the crystal and begin operation. once the pll is locked, all the outputs derived from it will be synchronized and output phase adju stments can then be applied if desired. serial control port description serial control port configuration description the device has a serial control port capable of responding as a slave in an i 2 c compatible configuration, to allow access to any of the internal registers for device programming or examination of internal status. all registers are configured to have default values. see th e specifics for each register for details. en en en 0 0 q0 dis en en 0 1 en dis en 1 0 dis dis dis 1 1 q1 fclk 4 osel[1] osel[0]
12 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet i 2 c mode operation the i 2 c interface is designed to fully support v1.2 of the i 2 c specification for normal and fast mode operation. the device acts as a slave device on the i 2 c bus at 100khz or 400khz using the address defined in the serial interface control register (0006h), as modified by the s_a0 & s_a1 input pin settings. the interface accepts byte-oriented block write and block read operations. two address bytes specify the register address of the byte position of the first register to write or read. data bytes (registers) are accessed in sequential order fr om the lowest to the highest byte (most significant bit first). read and write block transfers can be stopped after any complete byte transfer. duri ng a write operation, data will not be moved into the registers until the stop bit is received, at which point, all data received in the b lock write will be written simultaneously. for full electrical i 2 c compliance, it is recommended to use external pull-up resistors for sdata and sclk. the internal pull-up resistors have a size of 51k ? ? ? ? ? current read s dev addr + r a data 0 a data 1 a a data n p sequential read s dev addr + w a data 0 a data 1 a a data n p offset addr msb a sr dev addr + r a sequential write s dev addr + w a data 0 p a data 1 a a data n a from master to slave from slave to master offset addr lsb a offset addr msb a offset addr lsb a s=start sr = repeated start a=acknowledge a=non \ acknowledge p=stop
13 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet register descriptions table 4: register blocks register ranges offset (hex) register block description 0000 - 0001 reserved 0002 - 0005 device id control registers 0006 - 0007 serial interface control registers 0008 - 002f digital pll control registers 0030 - 0038 gpio control registers 0039 - 003e output driver control registers 003f - 004a output divider contro l registers (integer portion) 004b - 0056 reserved 0057 - 0062 output divider contro l registers (fractional portion) 0063 - 0067 output divider source control registers 0068- 006b analog pll control registers 006c - 0070 power-down & lock alarm control registers 0071 - 0078 input monitor control registers 0079 interrupt enable register 007a - 007b factory setting registers 007c - 01ff reserved 0200 - 0201 interrupt status registers 0202 - 020b reserved 020c general-purpose input status register 020d - 0212 global interrupt and boot status register 0213 - 03ff reserved
14 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 5: device id control register bit field locations and descriptions device id register control block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0002 rev_id[3:0] dev_id[15:12] 0003 dev_id[11:4] 0004 dev_id[3:0] dash_code [10:7] 0005 dash_code [6:0] 1 device id control register block field descriptions bit field name field type default value description rev_id[3:0] r/w 0h device revision. dev_id[15:0] r/w 0606h device id code. dash code [10:0] r/w 0b device dash code. decimal value assigned by idt to identify the configuration loaded at the factory. may be over-written by users at any time. table 6: serial interface control register bit field locations and descriptions serial interface control block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0006 0 uftadd[6:2] uftadd[1] uftadd[0] 0007 rsvd 1 device id control register block field descriptions bit field name field type default value description uftadd[6:2] r/w 11011b configurable portion of i 2 c base (bits 6:2) address for this device. uftadd[1] r/o 0b i 2 c base address bit 1. this address bit reflects the status of the s_a1 external input pin. see table 1. uftadd[0] r/o 0b i 2 c base address bit 0. this address bit reflects the status of the s_a0 external input pin. see table 1. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
15 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 7: digital pll input control register bit field locations and descriptions digital pll input control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0008 refsel[2:0] 1 0 1 1 1 0009 rsvd rsvd 000a rsvd 1 rsvd rsvd rsvd state[1:0] 000b rsvd pre0[20:16] 000c pre0[15:8] 000d pre0[7:0] 000e rsvd pre1[20:16] 000f pre1[15:8] 0010 pre1[7:0] digital pll input control register block field descriptions bit field name field type default value description refsel[2:0] r/w 000b input reference selection for digital pll: 000 = automatic selection 001 through 111 = reserved, do not use state[1:0] r/w 00b digital pll state machine control: 00 = run automatically 01 = force freerun state - set this if in synthesizer mode 10 = force normal state 11 = reserved pre0[20:0] r/w 000014h pre-divider ratio for input reference 0 (clk) when used by digital pll. pre1[20:0] r/w 000014h pre-divider ratio for input reference 1 (fbin) when used by digital pll. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
16 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 8: digital pll feedback control regi ster bit field locations and descriptions digital pll feedback control re gister block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0011 m1_0[23:16] 0012 m1_0[15:8] 0013 m1_0[7:0] 0014 m1_1[23:16] 0015 m1_1[15:8] 0016 m1_1[7:0] 0017 lckbw[3:0] acqbw[3:0] 0018 lckdamp[2:0] acqd amp[2:0] pllgain[1:0] 0019 rsvd rsvd rsvd rsvd 001a rsvd 001b rsvd 001c rsvd rsvd 001d rsvd 001e rsvd 001f ffh 0020 ffh 0021 ffh 0022 ffh 0023 rsvd rsvd rsvd rsvd rsvd fastlck 0024 lock[7:0] 0025 rsvd dsm_int[8] 0026 dsm_int[7:0] 0027 rsvd 0028 rsvd dsmfrac[20:16] 0029 dsmfrac[15:8] 002a dsmfrac[7:0] 002b rsvd 002c 01h 002d rsvd 002e rsvd 002f dsm_ord[1:0] dcxogain[ 1:0] rsvd dithgain[2:0]
17 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet digital pll feedback configuration register block field descriptions bit field name field type default value description m1_0[23:0] r/w 000014h m1 feedback divider ratio for input reference 0 (clk) when used by digital pll. m1_1[23:0] r/w 000014h m1 feedback divider ratio for input reference 1 (fbin) when used by digital pll. lckbw[3:0] r/w 0111b digital pll loop bandwidth while locked: 0000 = 0.2hz 0001 = 0.4hz 0010 = 0.8hz 0011 = 1.6hz 0100 = 3.2hz 0101 = 6.4hz 0110 = 12hz 0111 = 25hz 1000 = 50hz 1001 = 100hz 1010 = 200hz 1011 = 400hz 1100 = 800hz 1101 = 1.6khz 1110 = 6.4khz 1111 = reserved acqbw[3:0] r/w 0111b digital pll loop bandwidth while in acquisition (not-locked): 0000 = 0.2hz 0001 = 0.4hz 0010 = 0.8hz 0011 = 1.6hz 0100 = 3.2hz 0101 = 6.4hz 0110 = 12hz 0111 = 25hz 1000 = 50hz 1001 = 100hz 1010 = 200hz 1011 = 400hz 1100 = 800hz 1101 = 1.6khz 1110 = 6.4khz 1111 = reserved
18 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet lckdamp[2:0] r/w 011b damping factor for digital pll while locked: 000 = reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = reserved 111 = reserved acqdamp[2:0] r/w 011b damping factor for digital pll while in acquisition (not locked): 000 = reserved 001 = 1 010 = 2 011 = 5 100 = 10 101 = 20 110 = reserved 111 = reserved pllgain[1:0] r/w 01b digital loop filter gain settings for digital pll: 00 = 0.5 01 = 1 10 = 1.5 11 = 2 fastlck r/w 1b enables fast lock operation for digital pll: 0 = normal locking using lckbw & lckdamp fields in all cases 1 = fast lock mode using acqbw & acqdamp when not phase locked and lckbw & lckdamp once phase locked lock[7:0] r/w 3fh lock window size for digital pll. unsigned 2?s complement binary number in steps of 2.5ns, giving a total range of 640ns. do not program to 0. dsm_int[8:0] r/w 02ch integer portion of the delta-sigma modulator value. dsmfrac[20:0] r/w 181949h fractional portion of delta-sigma modulator value. divide this number by 2 21 to determine the actual fraction. digital pll feedback configuration register block field descriptions bit field name field type default value description
19 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet dsm_ord[1:0] r/w 11b delta-sigma modulator order for digital pll: 00 = delta-sigma modulator disabled 01 = 1st order modulation 10 = 2nd order modulation 11 = 3rd order modulation dcxogain[1:0] r/w 01b multiplier applied to instantaneous frequency error before it is applied to the digitally controlled oscillator in digital pll: 00 = 0.5 01 = 1 10 = 2 11 = 4 dithgain[2:0] r/w 000b dither gain setting for digital pll: 000 = no dither 001 = least significant bit (lsb) only 010 = 2 lsbs 011 = 4 lsbs 100 = 8 lsbs 101 = 16 lsbs 110 = 32 lsbs 111 = 64 lsbs rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. digital pll feedback configuration register block field descriptions bit field name field type default value description
20 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet the values observed on any gpio pins that are used as general purpose inputs are visible in the gpi[3:0] register that is locat ed at location 0x0219 near a number of other read-only registers. table 9: gpio control register bit field locations and descriptions gpio control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0030 rsvd gpio_dir[3:0] 0031 rsvd gpi3sel[2] gpi2sel [2] gpi1sel[2] gpi0sel[2] 0032 rsvd gpi3sel[1] gpi2sel [1] gpi1sel[1] gpi0sel[1] 0033 rsvd gpi3sel[0] gpi2sel [0] gpi1sel[0] gpi0sel[0] 0034 rsvd gpo3sel[2] gpo2sel [2] gpo1sel[2] gpo0sel[2] 0035 rsvd gpo3sel[1] gpo2sel [1] gpo1sel[1] gpo0sel[1] 0036 rsvd gpo3sel[0] gpo2sel [0] gpo1sel[0] gpo0sel[0] 0037 rsvd 0038 rsvd gpo[3:0] gpio control register block field descriptions bit field name field type default value description gpio_dir[3:0] r/w 0000b direction control for general-purpose i/o pins gpio[3:0]: 0 = input mode 1 = output mode gpi0sel[2:0] r/w 001b function of gpio[0] pin when set to input mode by gpio_dir[0] register bit: 000 = general purpose input (value on gpio[0] pin directly reflected in gpi[0] register bit) 001 = output enable control bit 0: osel[0], (refer to figure 4 for more details.) 010 = reserved 011 = reserved 100 through 111 = reserved gpi1sel[2:0] r/w 000b function of gpio[1] pin when set to input mode by gpio_dir[1] register bit: 000 = general purpose input (value on gpio[1] pin directly reflected in gpi[1] register bit) 001 = output enable control bit 1: osel[1], (refer to figure 4 for more details.) 010 through 111 = reserved gpi2sel[2:0] r/w 000b function of gpio[2] pin when set to input mode by gpio_dir[2] register bit: 000 = general purpose input (value on gpio[2] pin directly reflected in gpi[2] register bit) 001 = reserved 010 = reserved 011 = reserved 100 = reserved 101 through 111 = reserved
21 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet gpi3sel[2:0] r/w 000b function of gpio[3] pin when set to input mode by gpio_dir[3] register bit: 000 = general purpose input (value on gpio[3] pin directly reflected in gpi[3] register bit) 001 = reserved 010 = reserved 011 = reserved 100 through 111 = reserved gpo0sel[2:0] r/w 000b function of gpio[0] pin when set to output mode by gpio_dir[0] register bit: 000 = general purpose output (value in gpo[0] register bit driven on gpio[0] pin 001 = reserved 010 = reserved 011 = reserved 100 = reserved 101 = reserved 110 through 111 = reserved gpo1sel[2:0] r/w 000b function of gpio[1] pin when set to output mode by gpio_dir[1] register bit: 000 = general purpose output (value in gpo[1] register bit driven on gpio[1] pin 001 = loss-of-signal status flag for input reference 1 (fbin) reflected on gpio[1] pin 010 = reserved 011 = reserved 100 = reserved 101 = reserved 110 = reserved 111 = reserved gpo2sel[2:0] r/w 000b function of gpio[2] pin when set to output mode by gpio_dir[2] register bit: 000 = general purpose output (value in gpo[2] register bit driven on gpio[2] pin 001 = loss-of-signal status flag for input reference 0 (clk) reflected on gpio[2] pin 010 = reserved 011 = reserved 100 = reserved 101 through 111 = reserved gpo3sel[2:0] r/w 000b function of gpio[3] pin when set to output mode by gpio_dir[3] register bit: 000 = general purpose output (value in gpo[3] register bit driven on gpio[3] pin 001 = loss-of-lock status flag for digital pll reflected on gpio[3] pin 010 = reserved 011 = reserved 100 through 111 = reserved gpo[3:0] r/w 0000b output values reflect on pin gpio[3:0] when general-purpose output mode selected. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. gpio control register block field descriptions bit field name field type default value description
22 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 10: output driver control register bit field locations and descriptions output driver control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0039 rsvd rsvd 1 outen[1:0] 003a rsvd rsvd pol_q[1:0] 003b rsvd 003c rsvd 003d rsvd 1 rsvd rsvd 1 rsvd rsvd 003e outmode1[2:0] se_mode1 outmode0[2:0] se_mode0 output driver control register block field descriptions bit field name field type default value description outen[1:0] r/w 11b output enable contro l for clock outputs q[1:0], nq[1:0]: 0 = qn is in a high-impedance state 1 = qn is enabled as indicated in appropriate outmoden[2:0] register field pol_q[1:0] r/w 00b polarity of clock outputs q[1:0], nq[1:0]: 0 = qn is normal polarity 1 = qn is inverted polarity outmodem[2:0] r/w 011b output driver mode of operation for clock ou tputs q[1:0], nq[1:0]: 000 = high-impedance 001 = lvpecl 010 = lvds 011 = lvcmos 100 = hcsl 101 - 111 = reserved se_modem r/w 1b behavior of output pair qm, nq m when lvcmos operation is selected: (must be 0 if lvds or lvpec l output style is selected) 0 = qm and nqm are both the same frequency but inverted in phase 1 = qm and nqm are both the same frequency and phase rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
23 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 11: output divider control register (integer portion) bit field locations and descriptions output divider control register (integer portion) block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 003f rsvd ns1_q0[1:0] 0040 ns2_q0[15:8] 0041 ns2_q0[7:0] 0042 rsvd n_q1[17:16] 0043 n_q1[15:8] 0044 n_q1[7:0] 0045 rsvd n_fclk[17:16] 0046 n_fclk[15:8] 0047 n_fclk[7:0] 0048 rsvd 0049 rsvd 004a rsvd output divider control register (integer portion) block field descriptions bit field name field type default value description ns1_q0[1:0] r/w 01b 1st stage output div ider ratio for output clock q0, nq0: 00 = /5 01 = /6 10 = /4 11 = reserved ns2_q0[15:0] r/w 001dh 2nd stage output divider ratio for output clock q0, nq0. actual divider ratio is 2x the value written here. a value of 0 in this register will bypass the second stage of the divider. n_q1[17:0] r/w 00057h integer po rtion of output divider ratio for output clock q1, nq1: values of 0, 1 or 2 cannot be written to this register. actual divider ratio is 2x the value written here. n_fclk[17:0] r/w 002b8h integer portion of output divider ratio for output clock fclk, nfclk: values of 0, 1 or 2 cannot be written to this register. actual divider ratio is 2x the value written here. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
24 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 12: output divider control register (fractional portion) bit field locations and descriptions output divider control register (fractional portion) block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0057 rsvd nfrac_q1[27:24] 0058 nfrac_q1[23:16] 0059 nfrac_q1[15:8] 005a nfrac_q1[7:0] 005b rsvd nfrac_fclk[27:24] 005c nfrac_fclk[23:16] 005d nfrac_fclk[15:8] 005e nfrac_fclk[7:0] 005f rsvd 0060 rsvd 0061 rsvd 0062 rsvd output divider control register (fractional portion) block field descriptions bit field name field type default value description nfrac_q1[27:0] r/w 0000000h fractional portion of output divider ratio for output q1, nq1. actual fractional portion is 2x the value written here. fraction = (nfrac_q1 * 2) * 2 -28 nfrac_fclk[27:0] r/w 0000000h fractional portion of output divider ratio for output fclk, nfclk. actual fractional portion is 2x the value written here. fraction = (nfrac_fclk * 2) * 2 -28 rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
25 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 13: output clock source control register bit field locations and descriptions output clock source control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0063 pll_syn rsvd rsvd rsvd r svd rsvd clk_selfclk[1:0] 0064 rsvd 0065 rsvd 0066 rsvd rsvd rsvd rsvd 0067 rsvd rsvd rsvd rsvd output clock source control register block field descriptions bit field name field type default value description pll_syn r/w 0b output synchronization control for outputs derived from pll. setting this bit from 0->1 will cause the ou tput divider(s) for the affected outputs to be held in reset. setting this bit from 1->0 will release all t he output divider(s) for the affected outputs to run from the same point in time with th e coarse output phase adjustment reset to 0. clk_selfclk[1:0] r/w 00b clock source selection for outpu t pair fclk, nfclk: do not select input reference 0 or 1 if that input is faster than 250mhz: 00 = pll 01 = input reference 0 (clk) 10 = input reference 1 (fbin) 11 = crystal input rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
26 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet please contact idt through one of the methods listed on the last page of this datasheet for details on how to set these fields for a particular user configuration. table 14: analog pll control register bit field locations and descriptions analog pll control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0068 cpset[2:0] rs[1:0] cp[1:0] wpost 0069 rsvd rsvd tdc_dis syn_mode rsvd dlcnt dbitm 006a vcoman[2:0] dbit[4:0] 006b 001b rsvd analog pll control register block field descriptions bit field name field type default value description cpset[2:0] r/w 111b charge pump current setting for analog pll: 000 = 110a 001 = 220a 010 = 330a 011 = 440a 100 = 550a 101 = 660a 110 = 770a 111 = 880a rs[1:0] r/w 01b internal loop filter series resistor setting for analog pll: 00 = 330 ? ? ? ? cp[1:0] r/w 11b internal loop filter parallel capacitor setting for analog pll: 00 = 40pf 01 = 80pf 10 = 140pf 11 = 200pf wpost r/w 0b internal loop filter 2nd-pole setting for analog pll: 0 = rpost = 497 ? ? tdc_dis r/w 0b tdc disable control for pll: 0 = tdc enabled 1 = tdc disabled
27 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet syn_mode r/w 0b frequency synthesizer mode control for pll: 0 = pll jitter attenuates and translates one or more input references 1 = pll synthesizes output frequencies using only the crystal as a reference note that the state[1:0] field in the digital pll control register must be set to force free-run state. dlcnt r/w 1b digital lock count setting for analog pll: 0 = counter is a 20-bit accumulator 1 = counter is a 16-bit accumulator dbitm r/w 0b digital lock manual override setting for analog pll: 0 = automatic mode 1 = manual mode vcoman[2:0] r/w 001b manual lock mode vco selection setting for analog pll: 000 = vco0 001 = vco1 010 = vco2 011 = vco3 100 = vco4 101 = vco5 110 - 111 = reserved dbit[4:0] r/w 01011b manual mode digital lock control setting for vco in analog pll. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. analog pll control register block field descriptions bit field name field type default value description
28 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 15: power down control register bit field locations and descriptions power down control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 006c rsvd lckmode dbl_dis 006d rsvd rsvd clk_dis 006e rsvd 006f rsvd 1 rsvd q1_dis q0_dis 0070 rsvd dpll_dis dsm_dis calrst power down control register block fi eld descriptions bit field name field type default value description lckmode r/w 0b controls the behavior of the lol alarm deassertion: 0 = lol alarm deasserts once pll is locked 1 = lol alarm deasserts once pll is locked and output clocks are stable dbl_dis r/w 0b controls whether crystal input frequency is doubled before being used in pll: 0 = 2x actual crys tal frequency used 1 = actual crystal frequency used clk_dis r/w 0b disable control for differential clock input: 0 = input is enabled 1 = input is disabled qm_dis r/w 0b disable control for output qm, nqm (m = 0, 1): 0 = output qm, nqm functions normally 1 = all logic associated with output qm, nqm is disabled & driver in high-impedance state dpll_dis r/w 0b disable control for digital pll: 0 = digital pll enabled 1 = digital pll disabled dsm_dis r/w 0b disable control for delta-sigma modulator for analog pll: 0 = dsm enabled 1 = dsm disabled calrst r/w 0b reset calibration logic for analog pll: 0 = calibration logic for analog pll enabled 1 = calibration logic for analog pll disabled rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
29 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 16: input monitor control register bit field locations and descriptions input monitor control regi ster block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0071 rsvd los_0[16] 0072 los_0[15:8] 0073 los_0[7:0] 0074 rsvd los_1[16] 0075 los_1[15:8] 0076 los_1[7:0] 0077 rsvd 0078 rsvd input monitor control register block field descriptions bit field name field type default value description los_m[16:0] r/w 000b1h number of input monitoring clock periods before input reference m (m = 0 (clk), 1 (fbin)) is considered to be missed (soft alarm). minimum setting is 3. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. table 17: interrupt enable control register bit field locations and descriptions interrupt enable control register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0079 rsvd lol_en rsvd rsvd rsvd los1_en los0_en interrupt enable control register block field descriptions bit field name field type default value description lol_en r/w 0b interrupt enable control for loss-of-lock interrupt status bit: 0 = lol_int register bit will not affect status of nint output signal 1 = lol_int register bit will affect status of nint output signal losm_en r/w 0b interrupt enable control for loss-of-signal interrupt status bit for input reference (m = 0 (clk), 1 (fbin)): 0 = losm_int register bit will not affect status of nint output signal 1 = losm_int register bit will affect status of nint output signal rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
30 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet this register contains ?sticky? bits for tracking the status of the various alarms. whenever an alarm occurs, the appropriate i nterrupt status bit will be set. the interrupt status bit will remain asserted even after the original alarm goes away. the interrupt status bits r emain asserted until explicitly cleared by a write of a ?1? to the bit over the serial port. this type of functionality is referred to as read / wri te-1-to-clear (r/w1c). table 18: factory setting register bit field locations factory setting register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 007a 27h 007b rsvd rsvd rsvd rsvd rsvd rsvd table 19: interrupt status register bit field locations and descriptions interrupt status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 0200 rsvd lol_int rsvd rsvd rsvd los1_int los0_int 0201 rsvd interrupt status register block field descriptions bit field name field type default value description lol_int r/w1c 0b interrupt status bit for loss-of-lock: 0 = no loss-of-lock alarm flag on pll has occurred since the last time this register bit was cleared 1 = at least one loss-of-lock alarm flag on pll has occurred since the last time this register bit was cleared losm_int r/w1c 0b interrupt status bit for loss-of-signal on input reference (m = 0 (clk), 1 (fbin)): 0 = no loss-of-signal alarm flag on input reference m has occurred since the last time this register bit was cleared 1 = at least one loss-of-signal alarm flag on input reference m has occurred since the last time this register bit was cleared rsvd r/w - reserved. always write 0 to this bit location. read values are not defined. table 20: general purpose input status register bit field locations and descriptions global interrupt status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 020c rsvd gpi[3] gpi[2] gpi[1] gpi[0] general purpose input status register block field descriptions bit field name field type default value description gpi[3:0] r/o - shows current values on gpio[3:0] pins that are configured as general-purpose inputs. rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
31 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 21: global interrupt status register bit field locations and descriptions global interrupt status register block field locations address (hex) d7 d6 d5 d4 d3 d2 d1 d0 020d rsvd rsvd rsvd int 020e rsvd rsvd 020f rsvd rsvd 0210 rsvd rsvd rsvd rsvd 0211 rsvd rsvd rsvd rsvd rsvd rsvd rsvd rsvd 0212 rsvd global interrupt status register block field descriptions bit field name field type default value description int r/o - device interrupt status: 0 = no interrupt status bits that are enabled are asserted (nint pin released) 1 = at least one interrupt status bit that is enabled is asserted (nint pin asserted low) rsvd r/w - reserved. always write 0 to this bit location. read values are not defined.
32 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. supply voltage characteristics table 22: absolute ratings item rating supply voltage, v cc 3.63v inputs, v i osci other input 0v to 2v -0.5v to v cc + 0.5v outputs, v o (q[1:0], nq[1:0], fclk, nfclk) -0.5v to v ccox [a] + 0.5v a. v ccox denotes: v cco0 , v cco1 , v cco2 . o utputs, v o (gpio, sclk, sdata, nint) -0.5v to v cccs + 0.5v outputs, i o (q[1:0], nq[1:0], fclk, nfclk) continuous current surge current 40ma 65ma outputs, i o (gpio[3:0], sclk, sdata, nint) continuous current surge current 8ma 13ma junction temperature, t j 125 ? c storage temperature, t stg -65 ? c to 150 ? c table 23: power supply dc characteristics, v cc = 3.3v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v cc core supply voltage 3.135 3.3 3.465 v v cca analog supply voltage 3.135 3.3 v cc v v cccs control and status supply voltage 1.71 v cc v i cc core supply current [a] a. i cc, i cca and i cccs are included in i ee when output clocks configured for lvpecl logic levels. 39 50 ma i cccs control and status supply current [b] b. gpio [3:0], sdata, sclk, s_a1, s_a0, nint, nwp, nrst pins are floating. 36m a i cca analog supply current [a] 91 121 ma i ee power supply current [c] c. internal dynamic switching current at maximum f out is included. q[1:0], nq[1:0] configured for lvpecl logic levels; outputs unloaded [d] d. outputs enabled. 257 340 ma
33 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 24: power supply dc characteristics, v cc = 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v cc core supply voltage 2.375 2.5 2.625 v v cca analog supply voltage 2.375 2.5 v cc v v cccs control and status supply voltage 1.71 v cc v i cc core supply current [a] a. i cc, i cca and i cccs are included in i ee when output clocks configured for lvpecl logic levels. 39 50 ma i cccs control and status supply current [b] b. gpio [3:0], sdata, sclk, s_a1, s_a0, nint, nwp, nrst pins are floating. 3 5m a i cca analog supply current [a] 87 118 ma i ee power supply current [c] c. internal dynamic switching current at maximum f out is included. q[1:0], nq[1:0] configured for lvpecl logic levels; outputs unloaded [d] d. outputs enabled. 246 325 ma table 25: maximum output supply current, v cc = v cccs = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions v ccox [a] = 3.3v 5% a. v ccox denotes v cco0 , v cco1 , v cco2 . v ccox [a] = 2.5v 5% v ccox [a] = 1. 8v5% units lvpecl lvds hcsl lvcmos lvpecl lvds hcsl lvcmos lvcmos i cco0 [b] b. internal dynamic switching current at maximum f out is included. q0, nq0 output supply current outputs unloaded [c] c. outputs enabled. 41 50 41 44 35 42 36 35 30 ma i cco1 [b] q1, nq1 output supply current outputs unloaded [c] 55 64 55 55 48 57 47 52 43 ma i cco2 [b] fclk, nfclk output supply current outputs unloaded [c] n/a 66 n/a n/a n/a 58 n/a n/a n/a ma
34 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet dc electrical characteristics table 26: dc input characteristics, v cc = v ccox = 3.3v5% or 2.5v5% [a] a. v ccox denotes: v cco0 , v cco1 , v cco2 . symbol parameter test conditions minimum typical maximum units c in input capacitance [b] b. this specification does not apply to the osci or osco pins. 3.5 pf r pullup input pull-up resistor gpio[3:0], nrst, nwp, sdata, sclk 51 k ? 51 k ? 11.5 pf lvcmos: q1, fclk v ccox = 3.465v 13 pf lvcmos: q0 v ccox = 2.625v 10.5 pf lvcmos: q1, fclk v ccox = 2.625v 16 pf lvcmos: q0 v ccox = 1.89v 11 pf lvcmos: q1, fclk v ccox = 1.89v 13 pf lvds, hcsl or lvpecl: q0 v ccox = 3.465v or 2.625v 2.5 pf lvds, hcsl or lvpecl: q1, fclk v ccox = 3.465v or 2.625v 4.5 pf r out output impedance gpio[3:0] v cccs = 3.3v 26 ? 30 v cccs = 1.8v 42 lvcmos: q[1:0], nq[1:0], fclk v ccox = 3.3v 18 ? 22 v ccox = 1.8v 30
35 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 27: lvcmos/lvttl dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units v ih input high voltage nwp, nrst, gpio[3:0], sdata, sclk, s_a1, s_a0 v cccs = 3.3v 2.1 v cccs +0.3 v v cccs = 2.5v 1.7 v cccs +0.3 v v cccs = 1.8v 1.4 v cccs +0.3 v v il input low voltage nwp, nrst, gpio[3:0], sdata, sclk, s_a1, s_a0 v cccs = 3.3v -0.3 0.8 v v cccs = 2.5v -0.3 0.6 v v cccs = 1.8v -0.3 0.4 v i ih input high current s_a1, s_a0 v cccs = v in = 3.465v, 2.625v, 1.89v 150 ? a nrst, nwp, sdata, sclk v cccs = v in = 3.465v, 2.625v, 1.89v 5 ? a gpio[3:0] v cccs = v in = 3.465v, 2.625v, 1.89v 1ma i il input low current s_a1, s_a0 v cccs = 3.465v, 2.625v, 1.89v, v in = 0v -5 ? a nrst, nwp, sdata, sclk v cccs = 3.465v, 2.625v, 1.89v, v in = 0v -150 ? a gpio[3:0] v cccs = 3.465v, 2.625v, 1.89v, v in = 0v -1 ma v oh output high voltage sdata, [a] sclk, [a] nint [a] v cccs = 3.3v 5%, i oh = -5a 2.6 v gpio[3:0] v cccs = 3.3v 5%, i oh = -50a 2.6 v sdata, [a] sclk, [a] nint [a] v cccs = 2.5v 5%, i oh = -5a 1.8 v gpio[3:0] v cccs = 2.5v 5%, i oh = -50a 1.8 v sdata, [a] sclk, [a] nint [a] v cccs = 1.8v 5%, i oh = -5a 1.3 v gpio[3:0] v cccs = 1.8v 5%, i oh = -50a 1.3 v v ol output low voltage sdata, [a] sclk, [a] nint [a] v cccs = 3.3v 5%, 2.5v5%, or 1.8v5% i ol = 5ma 0.5 v gpio[3:0] v cccs = 3.3v 5%, 2.5v5%, or 1.8v5% i ol = 5ma 0.5 v a. use of external pull-up resistors is recommended.
36 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 28: differential input dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units i ih input high current clk, nclk; fbin, nfbin v cc = v in = 3.465v or 2.625v 150 ? i il input low current clk, fbin v cc = 3.465v or 2.625v, v in = 0v -5 ? nclk, nfbin v cc = 3.465v or 2.625v, v in = 0v -150 ? v pp peak-to-peak voltage [a] 0.15 1.3 v v cmr common mode input voltage [a], [b] v ee v cc -1.2 v a. v il should not be less than -0.3v. v ih should not be higher than v cc . b. common mode voltage is defined as the cross-point. table 29: lvpecl dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions v ccox [a] = 3.3v5% a. v ccox denotes v cco0 , v cco1 , v cco2 . v ccox [a] = 2.5v5% units minimum typical maximum minimum typical maximum v oh output high voltage [b] b. outputs terminated with 50 ? to v ccox ? 2v. v ccox - 1.3 v ccox - 0.8 v ccox - 1.4 v ccox - 0.9 v v ol output low voltage [b] v ccox - 1.95 v ccox - 1.75 v ccox - 1.95 v ccox - 1.75 v table 30: lvds dc ch aracteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c [a], [b] a. v ccox denotes v cco0 , v cco1 , v cco2 . b. terminated with 100 ? across qx and nqx. symbol parameter test conditions minimum typical maximum units v od differential output voltage 200 400 mv ? ? table 31: lvcmos dc characteristics, v cc = 3.3v 5% or 2.5v 5%, v ee = 0v, t a = -40c to 85c symbol parameter test conditions v ccox [a] = 3.3v5% a. v ccox denotes v cco0 , v cco1 , v cco2 . v ccox [a] = 2.5v5% v ccox [a] = 1.8v 5% units minimum typical maximum minimum typical maximum minimum typical maximum v oh output high voltage i oh = -8ma 2.6 1.8 1.1 v v ol output low voltage i ol = 8ma 0.5 0.5 0.5 v
37 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 32: input frequency characteristics, v cc = 3.3v5% or 2.5v5%, t a = -40c to 85c symbol parameter test conditions minimum typical maximum units f in input frequency [a] a. for the input reference frequency, the divider values must be set for the vco to operate within its supported range. osci, osco using a crystal (see table 33 for crystal characteristics) 10 50 mhz over-driving crystal input doubler logic enabled [b] b. for optimal noise performance, the use of a quartz crystal is recommended. refer to overdriving the xtal interface in the applications information section. 10 62.5 mhz over-driving crystal input doubler logic disabled [b] 10 125 mhz clk, nclk; fbin, nfbin 0.008 875 mhz f pd phase detector frequency [c] c. pre-dividers must be used to divide the input reference frequency down to a f pd valid frequency range. 0.008 8 mhz f sclk serial port clock sclk (slave mode) i 2 c operation 100 400 khz table 33: crystal characteristics parameter test conditions minimum typical maximum units mode of oscillation fundamental frequency 10 50 mhz equivalent series resistance (esr) 15 30 ? load capacitance (c l ) 12 pf frequency stability (total) -100 100 ppm
38 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet ac electrical characteristics table 34: ac characteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5%, 2.5v 5% or 1.8v 5% (1.8v only supported fo r lvcmos outputs), t a = -40c to 85c [a], [b] symbol parameter test conditions minimum typical maximum units f vco vco operating frequency 3000 4000 mhz f out output frequency lvpecl, lvds, hcsl integer divide ratio 0.008 1000 mhz q0, q1, fclk outputs non-integer divide 0.008 400 mhz lvcmos 0.008 250 mhz t r / t f output rise and fall times lvpecl 20% to 80% 320 520 ps lvds 20% to 80%, v ccox = 3.3v 160 320 ps 20% to 80%, v ccox = 2.5v 200 400 ps hcsl 20% to 80% 280 470 ps lvcmos [c], [d] 20% to 80%, v ccox = 3.3v 240 310 ps 20% to 80%, v ccox = 2.5v 260 330 ps 20% to 80%, v ccox = 1.8v 350 550 ps sr output |slew rate lvpecl measured on differential waveform, 150mv from center 15 v / n s lvds measured on differential waveform, 150mv from center, v ccox = 2.5v 0.5 4 v/ns measured on differential waveform, 150mv from center, v ccox = 3.3v 0.5 5 v/ns hcsl measured on differential waveform, 150mv from center, v ccox = 2.5v, f out ? 156.25mhz 1.5 5 v/ns measured on differential waveform, 150mv from center, v ccox = 3.3v, f out ? 156.25mhz 2.5 6.5 v/ns odc output duty cycle [e] lvpecl, lvds, hcsl f out ? 666.667mhz 45 50 55 % lvpecl, lvds, hcsl f out > 666.667mhz 40 50 60 % lvcmos 40 50 60 % spo static phase offset [f] default configuration 431 ps ? spo static phase offset variation [f] default configuration -200 200 ps
39 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet ? ssb (1k) single sideband phase noise [f] 1khz q0, nq0 -131 dbc/hz q1, nq1 -124 dbc/hz ? ssb (10k) 10khz q0, nq0 -148 dbc/hz q1, nq1 -141 dbc/hz ? ssb (100k) 100khz q0, nq0 -157 dbc/hz q1, nq1 -151 dbc/hz ? ssb (1m) 1mhz q0, nq0 -165 dbc/hz q1, nq1 -158 dbc/hz ? ssb (5m) 5mhz q0, nq0 -165 dbc/hz q1, nq1 -161 dbc/hz spurious limit at offset [f] > 800khz default configuration -64.5 dbc t startup startup time [g] internal otp star tup from v cc >80% to first output clock edge 110 150 ms a. v ccox denotes v cco0 , v cco1 , v cco2 . b. electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the de vice is mounted in a test socket with maintained transverse airflow greater than 500lfpm. the device will meet specifications after the rmal equilibrium has been reached under these conditions. c. appropriate se_mode bit must be configured to select phase-aligned or phase-inverted operation. d. all q and nq outputs in phase-inverted operation. e. characterized in pll mode. duty cycle of bypassed signals (input reference clocks or crystal input) is not adjusted by the de vice. f. characterized with default configuration. g. this parameter is guaranteed by design. table 34: ac characteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5%, 2.5v 5% or 1.8v 5% (1.8v only supported fo r lvcmos outputs), t a = -40c to 85c [a], [b] (cont.) symbol parameter test conditions minimum typical maximum units
40 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet table 35: hcsl ac characteristics, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5% or 2.5v 5%, t a = -40c to 85c [a], [b] symbol parameter test conditions minimum typical maximum units v rb ring-back voltage margin [c], [d] -100 100 mv t stable time before v rb is allowed [c], [d] 500 ps v max absolute max. output voltage [e], [f] 1150 mv v min absolute min. output voltage [e], [g] -300 mv v cross absolute crossing voltage [h], [i] 200 500 mv ? v cross total variation of v cross over all edges [h], [j] 140 mv a. electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the de vice is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. b. v ccox denotes v cco0 , v cco1 , v cco2 . c. measurement taken from differential waveform. d. t stable is the time the differential clock must maintain a minimum 150mv differential voltage after rising/falling edges before it is allowed to drop back into the v rb 100mv differential range. e. measurement taken from single ended waveform. f. defined as the maximum instantaneous voltage including overshoot. g. defined as the minimum instantaneous voltage including undershoot. h. measured at crossing point where the instantaneous voltage value of the rising edge of qx equals the falling edge of nqx. i. refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to all crossing points for this measurement. j. defined as the total variation of all crossing voltages of rising qx and falling nqx, this is the maximum allowed variance in v cross for any particular system. table 36: typical rms phase jitter, v cc = 3.3v 5% or 2.5v 5%, v ccox = 3.3v 5%, 2.5v 5% or 1.8v 5% (1.8v only supported fo r lvcmos outputs), t a = -40c to 85c [a] a. v ccox denotes v cco0 , v cco1 , v cco2 . symbol parameter test conditions typical units tjit( ? ) rms phase jitter [b] (random) b. it is recommended to use idt?s timing commander software to program the device for optimal jitter performance. q0 default configuration 375 fs q1 default configuration 382 fs
41 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet typical phase noise (q 0, default configuration) figure 6: typical phase noise plot noise power dbc hz offset frequency (hz)
42 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet typical phase noise (q 1, default configuration) figure 7: typical phase noise plot noise power dbc hz offset frequency (hz)
43 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet applications information recommendations for unused input and output pins inputs: clk/nclk input for applications not requiring the use of one or more reference clock inputs, both clk and nclk can be left floating. though no t required, but for additional protection, a 1k ? crystal inputs for applications not requiring the use of the crystal oscillator input, both osci and osco can be left floating. though not req uired, but for additional protection, a 1k ? lvcmos control pins all control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional pr otection. a 1k ? outputs: lvpecl outputs any unused lvpecl output pair can be left floating. we recommend that there is no trace attached. both sides of the differentia l output pair should either be left floating or terminated. lvds outputs any unused lvds output pair can be either left floating or terminated with 100 ? lvcmos outputs any lvcmos output can be left floating if unused. there should be no trace attached. hcsl outputs all unused differential outputs can be left floating. we recommend that there is no trace attached. both sides of the different ial output pair should either be left floating or terminated.
44 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet overdriving the xtal interface the osci input can be overdriven by an lvcmos driver or by one side of a differential driver through an ac coupling capacitor. the osco pin can be left floating. the amplitude of the input signal should be between 500mv and 1.8v and the slew rate should not be le ss than 0.2v/ns. for 3.3v lvcmos inputs, the amplitude must be reduced from full swing to at least half the swing in order to prevent s ignal interference with the power rail and to reduce internal noise. figure 8 shows an example of the interface diagram for a high speed 3.3v lvcmos driver. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (r s) equals the transmission line impedance. in addition, matched termination at the crystal input will attenuate the signal in half. this can be done in one of two ways. first, r1 and r2 in parallel should equal the transmission line impedance. for most 50 ? ? ? figure 9 shows an example of the interface diagram for an lvpecl driver. this is a standard lvpecl termination with one side of the driver feeding the osci input. it is recommended that all components in the schematics be plac ed in the layout. though some components might not be used, they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a quartz crystal as the input. figure 8: general diagram for lvcmos driver to xtal input interface figure 9: general diagram for lvpecl driver to xtal input interface lvcmos_driver zo = 50 rs zo = ro + rs ro r2 100 r1 100 vcc osco osci c1 0.1 f lvpecl_driver zo = 50 r2 50 r3 50 c2 0.1 f osco osci zo = 50 r1 50
45 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet wiring the differential input to accept single-ended levels figure 10 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be lo cated as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the inpu t will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impeda nce. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even thou gh the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specif ies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larg er, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. suggest edge rate faster than 1v/ns. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datashe et specifications are characterized and guaranteed by using a differential signal. figure 10: recommended schematic for wiring a differential input to accept single-ended levels
46 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet 3.3v differential clock input interface clk/nclk accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 11 to figure 15 show interface examples for the clk, nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 11 , the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termi nation recommendation. figure 11: clk/ nclk input driven by an idt open emitter lvhstl driver figure 12: clk/ nclk input driven by a 3.3v lvpecl driver figure 13: clk/ nclk input driven by a 3.3v hcsl driver figure 14: clk/ nclk input driven by a 3.3v lvpecl driver figure 15: clk/ nclk input driven by a 3.3v lvds driver r1 50 r2 50 1.8v zo = 50 zo = 50 clk nclk 3.3v lvhstl idt lvhstl driver differential input hcsl *r3 *r4 clk nclk 3.3v 3.3v differential input
47 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet 2.5v differential clock input interface clk/nclk accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figure 16 to figure 20 show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the dr iver termination requirements. for example, in figure 16 , the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 16: clk/ nclk input driven by an idt open emitter lvhstl driver figure 17: clk/ nclk input driven by a 2.5v lvpecl driver figure 18: clk/ nclk input driven by a 2.5v hcsl driver figure 19: clk/ nclk input driven by a 2.5v lvpecl driver figure 20: clk/ nclk input driven by a 2.5v lvds driver r1 50 ? r2 50 ? 1.8v zo = 50 ? zo = 50 ? clk nclk 2.5v lvhstl idt open emitter lvhstl driver differential input hcsl *r3 33 *r4 33 clk nclk 2.5v 2.5v zo = 50 zo = 50 differential input r1 50 r2 50 *optional C r3 and r4 can be 0
48 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet lvds driver termination for a general lvds interface, the recommended value for the termination impedance (z t ) is between 90 ? ? ? ? figure 21 can be used with either type of output structure. figure 22 , which can also be used with both output types, is an optional termination with center tap capacitance to help filter common mode noise. the capacitor value should be approximately 50pf. if using a non-standard termina tion, it is recommended to contact idt and confirm if the output structure is current source or voltage source type. in addition, since the se outputs are lvds compatible, the input receiver?s amplitude and common-mode input range should be verified for compatibility with the outpu t. figure 21: standard lvds termination figure 22: optional lvds termination lvds driver z o ? z t z t lvds receiver lvds driver z o ? z t lvds receiver c z t 2 z t 2
49 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet termination for 3.3v lvpecl outputs the clock layout topology shown below is a typical termination for lvpecl outputs. the two different layouts mentioned are reco mmended only as guidelines. the differential outputs generate ecl/lvpecl compatible outputs. therefore, terminating resistors (dc current path to ground) o r current sources must be used for functionality. these outputs are designed to drive 50 ? figure 23 and figure 24 show two different layouts which are recommended only as guidelines. other suitable clock layouts may exist and it would be recommended that the board designers sim ulate to guarantee compatibility across all printed circuit and clock component process variations. figure 23: 3.3v lvpecl output termination figure 24: 3.3v lvpecl output termination r1 84 ? r2 84 ? 3.3v r3 125 ? r4 125 ? z o = 50 ? z o = 50 ? input 3.3v 3.3v + _
50 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet termination for 2.5v lvpecl outputs figure 25 and figure 27 show examples of termination for 2.5v lvpecl driver. these terminations are equivalent to terminating 50 ? figure 27 can be eliminated and the termination is shown in figure 26 . figure 25: 2.5v lvpecl driver termination example figure 26: 2.5v lvpecl driver termination example figure 27: 2.5v lvpecl driver termination example 2.5v lvpecl driver v cco = 2.5v 2.5v 2.5v 50 ? 50 ? r1 250 r3 250 r2 62.5 r4 62.5 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 + ? 2.5v lvpecl driver v cco = 2.5v 2.5v 50 ? 50 ? r1 50 r2 50 r3 18 + ?
51 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet hcsl recommended termination figure 28 is the recommended source termination for applications where the driver and receiver will be on a separate pcbs. this terminat ion is the standard for pci express? and hcsl output types. all traces should be 50 ? ? figure 28: recommended source termination (where the driver and receiver will be on separate pcbs) figure 29 is the recommended termination for applications where a point-to-point connection can be used. a point-to-point connection contains both the driver and the receiver on the same pcb. with a matched termination at the receiver, transmission-line reflec tions will be minimized. in addition, a series resistor (rs) at the driver offers flexibility and can help dampen unwanted reflections. the o ptional resistor can range from 0 ? ? ? ? figure 29: recommended termination (where a point-to-point connection can be used) 0- 0.2" pc i e xpr e ss l1 l1 1-14" driver rs 0.5" max l3 l4 l2 l2 49. 9 +/- 5% 22 to 33 +/-5% rt l3 l4 l5 0.5 - 3.5" l5 connector pci express add-in card pci express 0-0.2" pci express 0-0.2" 0-18" l1 l1 rs driver 0.5" max l3 l3 l2 l2 49.9 +/- 5% 0 to 33 0 to 33 rt
52 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet vfqfn epad thermal release path in order to maximize both the removal of heat from the package and the electrical performance, a land pattern must be incorpora ted on the printed circuit board (pcb) within the footprint of the package corresponding to the exposed metal pad or exposed heat slug on the package, as shown in figure 30 . the solderable area on the pcb, as defined by the solder mask, should be at least the same size/shape as the exposed pad/slug area on the package to maximize the thermal/electrical performance. sufficient clearance should be designed on the pcb between the outer edges of the land pattern and the inner edges of pad pattern for the leads to avoid any shorts. while the land pattern on the pcb provides a means of heat transfer and electrical grounding from the package to the board thro ugh a solder joint, thermal vias are necessary to effectively conduct from the surface of the pcb to the ground plane(s). the land pattern m ust be connected to ground through these vias. the vias act as ?heat pipes?. the number of vias (i.e. ?heat pipes?) are application sp ecific and dependent upon the package power dissipation as well as electrical conductivity requirements. thus, thermal and electrical anal ysis and/or testing are recommended to determine the minimum number needed. maximum thermal and electrical performance is achieved when an array of vias is incorporated in the land pattern. it is recommended to use as many vias connected to ground as possible. it is also recommended that the via diameter should be 12 to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. this is desirable to avoid an y solder wicking inside the via during the soldering process which may result in voids in solder between the exposed pad/slug and the thermal la nd. precautions should be taken to eliminate any solder voids between the exposed heat slug and the land pattern. note: these recom mendations are to be used as a guideline only. for further information, please refer to the application note on the surface mount assembly of amkor?s thermally/ electrically enhance lead frame base package, amkor technology. figure 30: p.c. assembly for exposed pad thermal release path ? side view (drawing not to scale) schematic and layout information schematics for the 8t49n243 can be found on idt.com. please search for the 8t49n243 device and click on the link for evaluation board. the evaluation board user guide includes schematic and layout information. crystal recommendation this device was validated using fox 277lf series through-hole crystals including part # 277lf-40-18 (40mhz). if a surface mount crystal is desired, we recommend fox part #603-40-48 (40mhz). solder solder pin pin exposed heat slug pin pad pin pad ground plane land pattern (ground pad) thermal via
53 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet power dissipation and thermal considerations the 8t49n243 is a multi-functional, high speed device that targets a wide variety of clock frequencies and applications. since this device is highly programmable with a broad range of features and functionality, the power consumption will vary as these features and fun ctions are enabled. the 8t49n243 device is designed and characterized to operate within the ambient industrial temperature range of -40c to 85c. the ambient temperature represents the temperature around the device, not the junction temperature. when using the device in extrem e cases, such as maximum operating frequency and high ambient temperature, external air flow may be required in order to ensure a safe and reliable junction temperature. extreme care must be taken to avoid exceeding 125c junction temperature. the power calculation examples below are generated using maximum ambient temperature and supply voltage. for many applications, the power consumption will be much lower. please contact idt technical support for any concerns on calculating the power dissipatio n for your own specific configuration. power domains the 8t49n243 device has a number of separate power domains that can be independently enabled and disabled via register accesses (all power supply pins must still be connected to a valid supply voltage). figure 31 below indicates the individual domains and the associated power pins. figure 31: power domains power consumption calculation determining total power consumption involves several steps: 1. determine the power consumption using maximum current values for core and analog voltage supplies from table 23 and table 24 . 2. determine the nominal power consumption of each enabled output path which consists of: a. a base amount of power that is independent of operating frequency, as shown in table 38 through table 46 (depending on the chosen output protocol). b. a variable amount of power that is related to the output frequency. this can be determined by multiplying the output frequen cy by the fq_factor shown in table 38 through table 46 . 3. all of the above totals are summed. thermal considerations once the total power consumption has been determined, it is necessary to calculate the maximum operating junction temperature f or the device under the environmental conditions it will operate in. thermal conduction paths, air flow rate and ambient air temperatu re are factors that can affect this. the thermal conduction path refers to whether heat is to be conducted away via a heat-sink, via airflow o r via conduction into the pcb through the device pads (including the epad). thermal conduction data is provided for typical scenarios in table 37 below. please contact idt for assistance in calculating results under other scenarios. table 37: thermal resistance ? ja for 40-lead vfqfn, forced convection [a] a. note: assumes 5x5 grid of thermal vias under epad area for thermal conduction. ? ja by velocity meters per second 012 multi-layer pcb, jedec standard test boards 26.3c/w 23.2c/w 21.7c/w
54 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet current consumption data and equations table 38: 3.3v lvpecl output calculation table output fq_factor (ma/mhz) base_current (ma) q0 0.00660 32.9 q1 0.01088 44.4 table 39: 3.3v hcsl output calculation table output fq_factor (ma/mhz) base_current (ma) q0 0.00647 33.5 q1 0.01050 44.7 table 40: 3.3v lvds output calculation table output fq_factor (ma/mhz) base_current (ma) q0 0.00716 41.9 q1 0.01145 52.8 fclk table 41: 3.3v lvcmos output calculation table output base_current (ma) q0 31.3 q1 42.1 table 42: 2.5v lvpecl output calculation table output fq_factor (ma/mhz) base_current (ma) q0 0.00483 27.6 q1 0.00865 38.3 table 43: 2.5v hcsl output calculation table output fq_factor (ma/mhz) base_current (ma) q0 0.00425 27.7 q1 0.00827 38.5 table 44: 2.5v lvds output calculation table output fq_factor (ma/mhz) base_current (ma) q0 0.00483 36.0 q1 0.00906 46.3 fclk table 45: 2.5v lvcmos output calculation table output base_current (ma) q0 25.8 q1 36.0 table 46: 1.8v lvcmos output calculation table output base_current (ma) q0 22.8 q1 33.1
55 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet applying the values to the following equation will yield output current by frequency: qx current (ma) = fq_factor * frequency (mhz) + base_current where: qx current is the specific output current according to output type and frequency fq_factor is used for calculating current increase due to output frequency base_current is the base current for each output path independent of output frequency the second step is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient, using the following equation: t j = t a + ( ? ja * pd total ) where: t j is the junction temperature (c) t a is the ambient temperature (c) ? ja is the thermal resistance value from table 37 , dependent on ambient airflow (c/w) pd total is the total power dissipation of the 8t49n243 under usage conditions, including power dissipated due to loading (w). note that the power dissipation per output pair due to loading is assumed to be 27.95mw for lvpecl outputs and 44.5mw for hcsl outputs. when selecting lvcmos outputs, power dissipation through the load will vary based on a variety of factors including termination type and trace length. for these examples, power dissipation through loading will be calculated using c pd (found in table 26 ) and output frequency: pd out = c pd * f out * v cco 2 where: pd out is the power dissipation of the output (w) c pd is the power dissipation capacitance (f) f out is the output frequency of the selected output (mhz) v cco is the voltage supplied to the appropriate output (v)
56 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet power calculations example ? core supply current + control and status supply current = i cc + i cccs = 56ma (max) ? analog supply current, i cca = 121ma (max) ? output supply current: q0 current = 31.3ma q1 current = 42.1ma q2 current = 2.5 * 0.01145 + 52.8 = 52.8ma ? total output supply current = 126.2ma ? total device current: 56ma + 121ma + 126.2ma = 303.2ma ? total device power = 3.465v * 303.2ma = 1050.6mw ? power dissipated through output loading: lvcmos = 4.5mw 11.5pf * 10mhz * (3.465v) 2 * 1 output pair = 1.38mw 13pf * 20mhz * (3.465) 2 * 1 output pair = 3.12mw lvds = already accounted for in device power total power = 1050.6mw + 4.5mw = 1055.1mw= 1.06w with an ambient temperature of 85c, and no air flow, the junction temperature is: t j = 85c + 26.3c/w *1.06w = 112.9c this is below the limit of 125c. table 47: default configuration (3.3v core voltage) output output type frequency (mhz) v cco q0 lvcmos 10 3.3v q1 lvcmos 20 3.3v fclk lvds 2.5 3.3v
57 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet package dimensions figure 32: 40-lead vfqf n nl package outline www.idt.com d i t njo!1/31 njo!1/31
58 ?2016 integrated device technology, inc. november 8, 2016 8t49n243 datasheet figure 33: 40 lead vfqfn nl package outline, continued www.idt.com d i t
disclaimer integrated device technology, in c. (idt) reserves the right to modify t he products and/or specifications described h erein at any time, without notice, at idt's sole discretion. performance specifications and operating parameters of the described products are determi ned in an independent state and are not guaranteed to perform the same way when installed in customer products. the information contained herein is provided without representation or warr anty of any kind, whether express or impli ed, including, but not limited to, the suit ability of idt's products for any particular pur pose, an implied warrant y of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third parties. idt's products are not intended for use in applications involving extreme environmental conditions or in life support systems o r similar devices where the failure or malfunction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are trademarks or registered trademarks of idt and its subsidiaries in the u nited states and other countries. other trademarks used herein are the property of idt or their respective third party owners. for datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . copyright ?2016 integrated device te chnology, inc. all rights reserved. tech support www.idt.com/go/support sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com/go/sales corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa www.idt.com 8t49n243 datasheet marking diagram ordering information revision history part/order number marking package shipping packaging temperature 8t49n243nlgi iDT8T49N243NLGI 40 lead vfqfn, lead-free tray -40 ? ? 8t49n243nlgi8 iDT8T49N243NLGI 40 lead vfqfn, lead-free tape & reel -40 ? ? revision date description of change november 8, 2016 this is the first release of the 8t49n243 final datasheet. 1. line 1 and 2: part number. 2. line 3: ?#?: stepping ?yyww?: the last two digits of the year and week that the part was assembled ?$?: mark code idt8t49n24 3nlgi #yyww$ lot c00

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